1. The Field of the Invention
The present invention relates generally to semiconductor memory devices and more particularly to programmable memory devices.
2. The Background of the Invention
Non-volatile memory storage devices have become very ubiquitous in modern electronic applications. Non-volatile memories include read only memory (ROM) and various programmable and erasable variations therefrom, including programmable read only memory (PROM), erasable and electrically erasable programmable read only memory and other higher speed derivations therefrom. Another type of memory device includes a flash EPROM which has the capability of electrically erasing, programming, and reading a memory cell within the memory device.
A memory cell formed within a traditional flash EPROM has been traditionally formed using floating gate transistors, in which the data is stored in a cell by charging or discharging the floating gate. The floating gate has traditionally been comprised of conductive materials such as polysilicon which is insulated from the channel located between the drain and source of the transistor by a thin layer of insulative oxide or other insulating material. Under this traditional floating gate approach, data is stored in the memory cell by charging or discharging the floating gate. The floating gate is charged by applying a large positive voltage between the gate and the source or drain. Such an approach relies on the electron tunneling mechanism for storing the charge in the gate.
Alternatively, potentials such as electrical voltages may be applied to induce high energy electrons in the channel of a cell which are injected across the insulator of the floating gate. Such an alternative approach employs an avalanche mechanism for storing the charge within the floating gate. The voltage on the control gate or word line when divided by the coupling ratio of the memory cell results in a first voltage between the control gate and floating gate and a second voltage between the floating gate and the source or drain. An exemplary calculation of a 50% coupling ratio implies that half of the voltage applied to the control gate appears across the oxide between the floating gate and the source or drain. Such a voltage between the floating gate and the source or drain causes electrons to tunnel or to be injected into the floating gate through the thin insulator. When the floating gate is charged, the threshold voltage for causing the memory cell to conduct is increased above the voltage applied to the word line during a read operation. Thus, when the charged cell is addressed during a read operation, the cell does not conduct. The non-conducting state of the cell can be interrupted as a binary 1 or a 0, depending on the polarity of the sensing circuit.
In order to establish the opposite memory state, the floating gate is discharged through a typical tunneling process between the floating gate and the source or drain of the transistor, or between the floating gate and the substrate. That is to say, the floating gate may be discharged through the source by establishing a large positive voltage from the source to the gate while the drain is left at a floating potential. The high voltages used to charge and discharge a floating gate place significant design restrictions on flash memory devices, particularly as the cell dimensions and process specifications are reduced in size. Thus, the coupling ratio for the memory cells becomes a critical design parameter.
Memory cell designs, other thin those employing a floating gate, have been proposed. For example, ONO EPROM memory cells employ a trapping dielectric architecture as depicted in FIG. 1. The memory cell 10 includes a P-type silicon substrate 12 with an N+ drain 14 and an N+ source 16 implanted therein. In place of a traditional gate oxide, a non-conducting composite comprised of an oxide layer 28, a nitride layer 18, and another oxide layer 20, separate the polysilicon gate 22 from the channel 24. Oxide layer 28, nitride layer 18, and oxide layer 20 combine to form the ONO layer 26. It should be further pointed out that ONO layer 26 intentionally extends beyond the length of channel 24 out into the regions overlapping drain 14 and source 16. Such an overlap enables the trapping of the charge during the programming process as described below.
ONO memory cell 10 is programmed or written to by applying voltages to drain 14 and gate 22 while simultaneously grounding source 16. By way of example, a 10 volt potential may be applied to gate 22 with a 9 volt potential applied to drain 14. Such voltages generate electrical fields causing an inversion in channel 24 from source 16 to drain 14. Such a difference in potential in the presence of the electrical field causes electrons to migrate from source 16 and begin accelerating toward drain 14. In the migration toward drain 14 they gain energy and eventually gain sufficient energy to pass through oxide layer 20 and become trapped in nitride layer 18. The probability of such electrons traversing oxide layer 20 is maximized when there energy is also which occurs in a concentrated region nearest drain 14. Such high energy electrons, also known as hot electrons, become trapped in nitride layer 18 and remain concentrated or stored therein. Because nitride layer 18 is largely nonconductive, the electrons in nitride layer 18 do not spread throughout nitride layer 18 and remain in the localized trapping region near drain 14. It should be recalled that this is in contrast to memory cells implemented using floating gate technology wherein the retained charge is not locally trapped but rather distributed evenly across the entire gate region. Because of this distribution, the threshold for the entire gate increases as more charge is retained by the gate.
In contrast, for memory cells implemented according to FIG. 1 using a nitride layer or other similar low or nonconductive materials, the gate threshold voltage is altered only in the localized charge-trapping region. In both the floating gate or conductive gate implementation as well as in the low or nonconductive gate memory cell designs, an increase in the gate threshold voltage causes the current flowing through the channel to decrease. Such a reduction increases the programming time necessary for injecting an identifiable charge into the charge trapping region. In a ONO memory cell design, the programming time is reduced due to the localized charge trapping that is possible in a conductive floating gate memory cell implementation.
While the overlapping of the ONO composite 26 into the drain 14 and source 16 regions results in the creation of an e-field in the overlapping regions that enables charge trapping as described above, it would be desirable to provide a memory cell architecture that reduces the program and erase voltages and current necessary for trapping charge that is retainable and readable as a logic level.